(1) Field of the Invention
The present invention relates to a method of manufacturing a thin-film transistor (TFT) substrate that drives an active matrix liquid crystal display device and an organic electroluminescence (EL) display device, and in particular, to a method of manufacturing a thin-film transistor substrate including a channel layer with a bilayer structure of a microcrystal semiconductor layer and an amorphous semiconductor layer.
(2) Description of the Related Art
In recent years, organic EL display devices using organic EL elements are attracting attention, as one type of next-generation flat panel displays that replace liquid crystal display devices. The organic EL display devices are current-driven devices and different from voltage-driven liquid crystal display devices. In order to use the organic EL display devices as active matrix display devices, TFTs included in driving circuit boards that drive organic EL elements need to have superior ON/OFF characteristics.
Conventionally, TFT substrates that are driving circuits of liquid crystal display devices have a single-layer structure of a channel layer made of an amorphous semiconductor or a polycrystalline semiconductor. Since the TFTs having the single-layer structure of the channel layer made of the amorphous semiconductor have a wide band-gap and thus have a lower OFF-state current, they have a problem of having a lower ON-state current due to low mobility.
On the other hand, since the TFTs having the single-layer structure of the channel layer made of the polycrystalline semiconductor have a higher ON-state current due to high mobility unlike the TFT substrates having the single-layer structure of the channel layer made of the amorphous semiconductor, they have a problem of having a higher OFF-state current due to defects and the grain boundary in the polycrystalline semiconductor.
In order to solve these problems, a thin-film semiconductor device including a channel layer with a bilayer structure of a polycrystalline semiconductor layer and an amorphous semiconductor layer is suggested (for example, see Hatzopoulos et al., IEEE ELECTRON DEVICE LETTERS, VOL 28, NO. 9, SEPTEMBER 2007). It is said that since the advantages of both of the polycrystalline semiconductor layer and the amorphous semiconductor layer in the bilayer structure mutually work, ideally the following characteristics can be obtained: the ON-state current of the channel layer with the bilayer structure is higher than that of the single-layered channel layer made of the amorphous semiconductor, and the OFF-state current of the channel layer with the bilayer structure is lower than that of the single-layered channel layer made of the polycrystalline semiconductor.
However, Japanese Unexamined Patent Application Publication No. 8-088371 discloses the slight appearance of oxide silicon (SiOx) and an impurity-doped layer due to contamination, in a boundary between an intrinsic semiconductor layer and an impurity-doped semiconductor layer and a boundary between an impurity-doped semiconductor layer and source, and drain electrodes. The impurity-doped layer increases a contact resistance, and particularly degrades the current when the drain voltage is low. Thus, a problem occurs: the characteristics of the drain current with respect to the drain voltage, that is, the ohmic characteristics in a channel region are degraded. When such a TFT with the degraded ohmic characteristics is used as a switching element that is a display driving means for a liquid crystal display device, gradation defects appear in data lines, which may cause point defects on a display device.
Even when a TFT substrate includes a channel layer with the bilayer structure of the polycrystalline semiconductor layer and the amorphous semiconductor layer, an unintended native oxide layer is formed in a boundary between the polycrystalline semiconductor layer and the amorphous semiconductor layer, due to differences in manufacturing processes between these layers, as formed in the boundary between the intrinsic semiconductor layer and the impurity-doped semiconductor layer. For example, when a lower semiconductor layer is modified into a polycrystalline semiconductor layer with laser irradiation or annealing, since the lower semiconductor layer is exposed to air, the native oxide layer is formed on the surface of the in-process lower semiconductor layer. Furthermore, even a TFT substrate with a bilayer structure of Channel Etching Stopper (CES) layers needs to come in contact with air, and the native oxide layer is formed between the layers. Accordingly, the transistor characteristics, such as the ON-state current, are degraded, and the display quality decreases.
The examples of a process of removing the native oxide layer in a boundary between the polycrystalline semiconductor layer and the amorphous semiconductor layer included in the channel layer includes exposing the surface of the polycrystalline semiconductor layer to hydrogen plasma or argon plasma after forming the polycrystalline semiconductor layer and immediately before forming the amorphous semiconductor layer.
However, although the process of removing the native oxide layer produces a certain advantage, it is difficult to check the remaining state of the native oxide layer during the removing process and evaluate it. Furthermore, checking the remaining state of the native oxide layer after the removing process is not appropriate.
Furthermore, excessive exposure of the surface of the polycrystalline semiconductor layer to hydrogen plasma or argon plasma in view of the incapability of checking the remaining state of the native oxide layer during the removing process causes the semiconductor layer and the CES layers to be peeled off and produces the negative impact on the characteristics, such as amorphization on the surface of the semiconductor layer and degradation in the CES layers.
On the other hand, when the native oxide layer remains due to the incapability of checking the remaining state of the native oxide layer during the removing process, the rate of a post-process of insularly etching the semiconductor layers with the bilayer structure varies, the timing to stop the etching becomes instable, and the TFTs becomes non-uniform.
As described above, the semiconductor characteristics are further degraded with the remaining native oxide layer and the excessive removing process, and a TFT substrate with such semiconductor characteristics becomes a defective part. As a result, problem arises, such as decrease in the yield and higher manufacturing cost.
The present invention has been conceived in view of the problems, and has an object of providing a method of manufacturing a TFT substrate including a channel layer with a bilayer structure of a polycrystalline semiconductor layer and an amorphous semiconductor layer in order not to degrade the characteristics of the transistors without checking the remaining state of a native oxide layer in a boundary between the two semiconductor layers during removing the native oxide layer.